The present invention relates in general to cache operations and, more particularly, to the handling of corrupted background data in an out of order execution environment to avoid instruction processing damage.
A computer system typically includes a processor coupled to a hierarchical storage system. The hardware can dynamically allocate parts of memory within the hierarchy for addresses deemed most likely to be accessed soon. The type of storage employed in each staging location relative to the processor is normally determined by balancing requirements for speed, capacity, and costs.
A commonly employed memory hierarchy includes a special, high-speed memory known as cache, in addition to the conventional memory which includes main memory and bulk memory. Cache memory may be arranged in a variety of configurations.
Multiple levels of cache memory may be present in computer systems. For example, L1 cache, from Level 1 cache, is known as the primary cache and is built into a microprocessor. L1 cache is the smallest and fastest cache level. L2 cache, short for Level 2 cache, is a second level of cache that is larger and slower compared to L1 cache. L2 cache, also called the secondary cache, may be found on a separate chip from the microprocessor chip or may be incorporated into a microprocessor chip's architecture. Other layers of cache, such as L3 or Level 3 cache, may also be implemented on the microprocessor chip or on a separate chip.
Caches may have built-in failure checks and may use either parity or error correction code (ECC) methods for detecting errors. For example, parity checks require an extra bit for every 8 bits of data and check for memory errors using even parity or odd parity checks. For even parity, when the 8 bits in a byte receive data, the chip adds up the total number of 1 s. If the total number of 1 s is odd, the parity bit is set to 1. If the total is even, the parity bit is set to 0. Odd parity works the same way, but the parity bit is set to 1 when the total number of 1 s in the byte is even. When the data is read from the cache, each byte is parity checked. The parity for the 8 bits is calculated again and compared against the stored parity bit. If they mismatch the chip knows that there is an error somewhere in the 8 bits and dumps the data.
Parity checking can detect all single bit errors. However, parity checking does nothing to correct the errors. If a byte of data does not match its parity bit, then the data are discarded and the system must recover. This problem can reduce cache efficiency and performance.
Some memory caches use a form of error checking known as error-correction code (ECC). Like parity, ECC uses additional bits to monitor the data in each byte. The difference is that ECC uses several bits for error checking instead of one. ECC uses a special algorithm not only to detect single bit errors, but actually correct them as well.
Modern microprocessors use several layers of caches to hide memory latency from the core processing units. Usually the lower level cache hierarchies (e.g., L1 cache) use parity checking to detect data errors. Higher cache hierarchies (e.g., L2 cache, L3 cache) usually implement ECC to detect and correct data errors. If modified data is lost or gets corrupted on its way through the cache hierarchies, this is a major error and causes IPD (Instruction Processing Damage). This is why even though the L1 cache is only parity protected, the L1 store queue is ECC protected. A store queue (like the L1 store queue) is collecting store requests from the core and acts like a buffer that can be written faster than the actual L1 cache.